Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. The task of all routers is the same—routers are given some pre-existing polygons consisting of pins on cells and optionally some pre-routes from the placers to create geometries so that all pins assigned to different nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing.
Timing closure has become increasingly difficult and presents some profound challenges in electronic circuit designs. The main goal of computer-aided design simulations is obtaining desired device electrical characteristics. Nonetheless, geometric dimensions and profiles of features of an electronic circuit design often have significant impact on the device electrical characteristics. The device dimensions which may have significant impact on the electrical characteristics include, for example, gate oxide thickness, gate width and length, shape of the poly gate at the bottom, and spacer width. As device geometry shrinks, semiconductor fabrication processes require more complex techniques to meet the design goals such as lower power supply, thinner gate oxides, shorter channel length, higher body doping concentration, and thinner silicon films. More importantly, the timing delay caused by the wires becomes more significant and can no longer be ignored.
As the device size continues to shrink and the clock frequency nevertheless increases, particularly into the deep-submicron regime, the electrical properties of wires or conductors become more prominent, and integrated circuit chips are more susceptible to breakdowns during fabrication due to, for example, the antenna effect or due to wear out or degradation over time due to, for example, electro-migration. Some prior methods propose prioritizing the nets and forcing shorter wire lengths among the high-priority, timing critical nets. However, making certain wires shorter usually comes at the expense of making other wires longer. Some other prior methods use larger gates with bigger transistors and higher drive strengths to charge the capacitance of wires more quickly and therefore making the path faster to maintain timing correctness without overly shortening some wires while lengthening others. However, there exists one problem for these methods. In electronic designs, the actual wire lengths are usually not known until some gates are physically in place occupying certain area(s) in the electronic circuit. Nonetheless, because larger gates also have larger capacitance and thus increases power and perhaps timing delay, the above method does not satisfactorily solve the problems caused by increasingly shrinking feature sizes.
Moreover, the continual effort to scale down electronic design features to the deep submicron region requires multilevel interconnection architecture to minimize the timing delay due to parasitic resistance and capacitance. As the devices shrinks to smaller sizes, the delay caused by the increased R-C time constant becomes more significant over the delay caused by the actual wire length. In order to reduce the R-C time constant, interconnect materials with lower resistivity and interlayer films with lower capacitance are required. However, the use of low-k dielectric material also aggravates the electro-migration problem due to the poor thermal conductivity of these low-k dielectric materials.
In addition, modern electronic designs are often implemented with multiple hierarchical levels. For a hierarchical electronic design, accurate timing analyses are very important. For faster convergence of the entire chip implementation, reassembly is typically used to iteratively perform block level timing constraints with hierarchical partitioning and time budgeting and block reassembly to synchronize changes made at the block level, until a good flat chip timing is achieved. Nonetheless, the reassembly flow requires expensive iterations, each of which requires full chip assembly and timing assessment. The reassembly flow may also lead to degraded post assembly timing and hence longer time to market.
In addition, in a typical reassembly flow, each block in the chip implementation is implemented independent of the changes, such as transformations for timing optimization or changes in timing constraints, made in other blocks. For interface paths, the assigned budget for block implementation may get exhausted with a given reference clock before the interface paths are properly closed and thus leaving no room for further optimization. As a result, this conventional approach may have to go through the expensive reassembly cycles with re-budgeting. In some cases, an interface path may be made a multi-cycle path from a single-cycle path or vice-versa during the independent implementation of a block such that the distributed budgets are rendered defunct because the original budgets usually lead to highly optimistic or highly pessimistic timing due to the increased or reduced cycles on the interface path. Moreover, if an interface is made a false path then its chip top level representation also becomes a false path. Nonetheless, this information is communicated to other blocks only after reassembly due to the independent implementation of the blocks and thus may lead to non-useful area claimed.
Thus, there exists a need for a method, a system, and an article of manufacture for synchronous hierarchical implementation of electronic circuit designs.